单片机广泛应用于商业外文翻译资料

 2022-08-17 03:08

(AT89C51中英文翻译对照)

Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.

1. Introduction

The 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical

applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially

prohibitive. Redesign costs can run as high as a $500K, much more if the fix means back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.

Intel Chandler Platform Engineering group provides post

silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.

The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil -lator disabling all other chip functions until the next hardware reset.

Pin Configurations

Block Diagram

Pin Description

VCC Supply voltage.

GND Ground.

Port 0

Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.

Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.

Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during program verification. External pullups are required during program verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 2 emits the high-ord

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单片机广泛应用于商业:诸如调制解调器,电动机控制系统,空调控制系统,汽车发动机和其他一些领域。这些单片机的高速处理速度和增强型外围设备集合使得它们适合于这种高速事件应用场合。然而,这些关键应用领域也要求这些单片机高度可靠。健壮的测试环境和用于验证这些无论在元部件层次还是系统级别的单片机的合适的工具环境保证了高可靠性和低市场风险。Intel 平台工程部门开发了一种面向对象的用于验证它的AT89C51汽车单片机多线性测试环境。这种环境的目标不仅是为AT89C51汽车单片机提供一种健壮测试环境,而且开发一种能够容易扩展并重复用来验证其他几种将来的单片机。开发的这种环境连接了AT89C51。本文讨论了这种测试环境的设计和原理,它的和各种硬件、软件环境部件的交互性,以及如何使用AT89C51。

1 介绍

8位AT89C51 CHMOS工艺单片机被设计用于处理高速计算和快速输入/输出。MCS51单片机典型的应用是高速事件控制系统。商业应用包括调制解调器,电动机控制系统,打印机,影印机,空调控制系统,磁盘驱动器和医疗设备。汽车工业把MCS51单片机用于发动机控制系统,悬挂系统和反锁制动系统。AT89C51尤其很好适用于得益于它的处理速度和增强型片上外围功能集,诸如:汽车动力控制,车辆动态悬挂,反锁制动和稳定性控制应用。由于这些决定性应用,市场需要一种可靠的具有低干扰潜伏响应的费用-效能控制器,服务大量时间和事件驱动的在实时应用需要的集成外围的能力,具有在单一程序包中高出平均处理功率的中央处理器。拥有操作不可预测的设备的经济和法律风险是很高的。一旦进入市场,尤其任务决定性应用诸如自动驾驶仪或反锁制动系统,错误将是财力上所禁止的。重新设计的费用可以高达500K美元,如果产品族享有同样内核或外围设计缺陷的话,费用会更高。另外,部件的替代品领域是极其昂贵的,因为设备要用来把模块典型地焊接成一个总体的价值比各个部件高几倍。为了缓和这些问题,在最坏的环境和电压条件下对这些单片机进行无论在部件级别还是系统级别上的综合测试是必需的。Intel Chandler平台工程组提供了各种单片机和处理器的系统验证。这种系统的验证处理可以被分解为三个主要部分。系统的类型和应用需求决定了能够在设备上执行的测试类型。

AT89C51提供以下标准功能:4k 字节FLASH闪速存储器,128字节内部RAM,32个I/O口线,2个16位定时/计数器,一个5向量两级中断结构,一个全双工串行通信口,片内振荡器及时钟电路。同时,AT89C51降至0Hz的静态逻辑操作,并支持两种可选的节电工作模式。空闲方式体制CPU的工作,但允许RAM,定时/计数器,串行通信口及中断系统继续工作。掉电方式保存RAM中的内容,但振荡器体制工作并禁止其他所有不见工作直到下一个硬件复位。

AT89C51方框图

引脚功能说明

·Vcc:电源电压

·GND:地

·P0口:P0口是一组8位漏极开路型双向I/O口,也即地址/数据总线复用。作为输出口用时,每位能吸收电流的方式驱动8个TTL逻辑门电路,对端口写“1”可作为高阻抗输入端用。

在访问外部数据存储器或程序存储器时,这组口线分时转换地址(低8位)和数据总线复用,在访问期间激活内部上拉电阻。

在Flash编程时,P0口接受指令字节,而在程序校验时,输出指令字节,校验时,要求外接上拉电阻。

·P1口:P1是一个带内部上拉电阻的8位双向I/O口,P1的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写“1”,通过内部的上拉电阻把端口拉到高电平,此时可作输入口。作为输入口使用时,因为内部存在上拉电阻,某个引脚被外部信号拉低时会输出一个电流(IIL)。

Flash编程和程序校验期间,P1接受低8位地址。

·P2口:P2是一个带有内部上拉电阻的8位双向I/O口,P2的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写“1”,通过内部的上拉电阻把端口拉到高电平,此时可作输入口。作为输入口使用时,因为内部存在上拉电阻,某个引脚被外部信号拉低时会输出一个电流(IIL)。

在访问外部程序存储器或16位四肢的外部数据存储器(例如执行MOVX @DPTR指令)时,P2口送出高8位地址数据,在访问8位地址的外部数据存储器(例如执行MOVX @ RI指令)时,P2口线上的内容(也即特殊功能寄存器(SFR)区中R2寄存器的内容),在整个访问期间不改变。

Flash编程和程序校验时,P2也接收高位地址和其他控制信号。

·P3口:P3是一个带有内部上拉电阻的8位双向I/O口,P3的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写“1”,通过内部的上拉电阻把端口拉到高电平,此时可作输入口。作为输入口使用时,因为内部存在上拉电阻,某个引脚被外部信号拉低时会输出一个电流(IIL)。

P3口除了作为一般的I/O口线外,更重要的用途是它的第二功能,如下所示:

端口引脚

第二功能

P3.0

RXD(串行输入口)

P3.1

TXD (串行输出口)

P3.2

INT0 (外中断0)

P3.3

INT1 (外中断1)

P3.4

T0 (定时/计数器0)

P3.5

T1 (定时/计数器1)

P3.6

WR (外部数据存储器写选通)

P3.7

RD (外部数据存储器读选通)

P3口还接收一些用于Flash闪速存储器编程和程序校验的控制信号。

·RST:复位输入。当振荡器工作时,RST引脚出现两个机器周期以上高电平将使单片机复位。

·ALE/PROG:当访问外部程序存储器或数据存储器时,ALE(地址锁存允许)输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器,ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号,因此它可对外输出时钟或用于定时目的。要注意的是,每当访问外部数据存储器时将跳过一个ALE脉冲。

对Flash存储器编程期间,该引脚还用于输入编程脉冲(PROG)。

如有必要,可通过对特殊功能寄存器(SFR)区中的8EH单元D0位置位,可禁止ALE操作。该位置位后,只有一条MOVX和MOVC指令ALE才会被激活。此外,该引脚会被微弱拉高,单片机执行外部程序时,应设置ALE无效。

·PSEN:程序存储允许输出是外部程序存储器的读选通型号,当89C51由外部存储器取指令(或数据)时,每个机器周期两次PSEN有效,即输出两个脉冲。在此期间,当访问外部数据存储器,这两次有效的PSEN信号不出现。

·EA/VPP:外部访问允许。欲使CPU仅访问外部程序存储器(地址为0000H—FFFFH),EA端必须保持低电平(接地)。需注意的是:如果加密位LB1被编程,复位时内部会锁存EA端状态。

如EA端为高电平(接Vcc端),CPU则执行内部程序存储器中的指令。

Flash存储器编程时,该引脚加上 12v的编程允许电源Vpp,当然这必须是该器件使用12v编程电压Vpp。

·XTAL1:振荡器反相放大器及内部时钟发生器的输入端。

·XTAL2:振荡器反相放大器的输出端

·时钟振荡器:

89C51中有一个用于构成内部振荡器的高增益反相放大器,引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。这个放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自激振荡器,振荡电路参见图5。

外接石英晶体或陶瓷谐振器及电容C1、C2接在放大器的反馈回路中构成并联振荡电路。对外接电容C1、C2虽没有十分严格的要求,但电容容量的大小会轻微影响振荡频率的高低、振荡器工作的稳定性、起振的难易程度及温度稳定性,如果使用石英晶体,我们推荐电容使用30Pfplusmn;10 Pf,而如使用陶瓷谐振器建议选择40Pfplusmn;10 Pf。

用户也可以采用外部时钟。采用外部时钟的电路如图5右图所示。这种情况下,外部时钟脉冲接到XTAL1端,即内部时钟发生器的输入端XTAL2则悬空。

·掉电模式:

在掉电模式下,振荡器停止工作,进入掉电模式的指令是最后一条被执行的指令,片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结。推出掉电模式的唯一方法是硬件复位,复位后将重新定义全部特殊功能寄存器但不改变RAM中的内容,在Vcc恢复到正常工作电平前,复位应无效,且必须保持一定时间以使振荡器重启动并稳定工作。

空闲和掉电模式外部引脚状态

模式

程序存储器

ALE

PSEN

P0

P1

P2

P3

空闲模式

内部

1

1

数据

数据

数据

数据

空闲模式

外部

1

1

悬空

数据

地址

数据

掉电模式

内部

0

0

数据

数据

数据

数据

掉电模式

外部

0

0

悬空

数据

数据

数据

·程序存储器的加密

89C51可使用对芯片上的3个加密位LB1、LB2、LB3进行编程(P)或不编程(U)来得到如下表所示的功能

程序加密位

保护类型

LB1

LB2

LB3

1

U

U

U

没有程序保护功能

2

P

U

U

禁止从外部程序存储器中执行MOVC 指令读取内部程序存储器的内容

3

P

P

U

除以上功能外,还禁止程序校验

4

P

P

P

除以上功能外,同时禁止外部执行

当加密位LB1被编程时,在复位期间,EA端的逻辑电平被采样并锁存,如果单片机上电后一直没有复位,则锁存起的初始值是一个随机数,且这个随机数会一直保存到真正复位为止。为使单片机上电后能正常工作,被锁存的EA电平值必须与该引脚当前的逻辑电平一致。此外,加密位只能通过整片擦除的方法清除。

·Flash闪速存储器的编程

89C51单片机内部有4K字节的Flash EPROM,这个Flash存储阵列出厂时已处于擦除状态(即所有存储单元的内容均为FFH),用户随时可对其进行编程。编程接口可接收高电压( 12v)或低电压(Vcc)的允许编程信号。低电压编程模式适合于用户在线编程系统,而高电压编程模式可与通用EPROM编程器兼容。

89C51单片机中,有些属于低电压编程方式,而有

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